此職位待遇面議！
職位一：
職位要求：
-?微電子、電子工程相關(guān)專業(yè)，大專以上學(xué)歷
-?擁有1?-?5年相關(guān)經(jīng)驗(yàn)
-?獨(dú)立或協(xié)作完成大型芯片模塊整合工作經(jīng)驗(yàn)優(yōu)先考慮
-?熟悉模擬版圖設(shè)計(jì)，有高壓版圖設(shè)計(jì)經(jīng)驗(yàn)優(yōu)先考慮
-?熟悉CMOS集成電路工藝流程，了解模擬電路的基本結(jié)構(gòu)，了解ESD/latchup原理和設(shè)計(jì)規(guī)則，了解芯片封裝要求,?熟悉器件和信號(hào)匹配的知識(shí)；
-?獨(dú)立完成版圖各項(xiàng)驗(yàn)證Calibre?(DRC,LVS,ERC,ESD,?ANT,?LATCH-UP,LPE)檢查
-?修改Calibre?DRC，LVS?runset文件者優(yōu)先考慮
-?熟悉Perl/TCL等編程語(yǔ)言優(yōu)先考慮
-?在快速推進(jìn)的工作環(huán)境中能夠同時(shí)處理多個(gè)工作任務(wù)
-?責(zé)任心強(qiáng)，做事積極主動(dòng)?,誠(chéng)信正直，踏實(shí)努力，具有較強(qiáng)的抗壓能力,?工作態(tài)度嚴(yán)謹(jǐn)
-?具有良好的溝通協(xié)調(diào)能力、學(xué)習(xí)能力、分析能力,?技術(shù)鉆研精神,?和團(tuán)隊(duì)合作能力
工作職責(zé)：
-?全制定制版圖設(shè)計(jì)
-?負(fù)責(zé)從底層模塊的版圖設(shè)計(jì)到頂層的布局布線和驗(yàn)證
-?負(fù)責(zé)項(xiàng)目的tapeout工作
職位二：
Job?Responsibilities:
-?Develop?DRC/LVS/LPE/PERC?deck?and?necessary?script?(experience?in?Calibre?is?an?advantage)
-?Responsible?for?QA?flow?to?ensure?the?quality?of?the?verification?command?file
-?Communicate?with?engineers?to?provide?solutions?on?verification?area
-?Learning?for?new?verification?tool?and?develop?related?deck
-?Performing?layout?of?custom?analog?circuit?blocks
-?Placing,?routing?and?integrating?digital?standard?cell?blocks
?
Job?Requirements:
-?Higher?Diploma?or?Bachelor?Degree?in?Electronics?Engineering?or?equivalent
-?2-3?years?of?relevant?experience?is?preferable
-?Experience?in?managing?foundry?process/?design?kit?is?an?advantage
-?Knowledge?in?ESD?/?Latchup?tools
-?Proficient?in?layout?design?and?the?associated?software
-?Knowledge?in?semiconductor/?fabrication?process?is?an?advantage
-?Proactive?and?willing?to?learn
-?Good?team?spirit?and?sound?communication?skills
-?Strong?passion?in?physical?design?area
-?Candidate?with?more?experiences?will?be?considered?as?Senior?Physical?Design?Engineer