崗位職責(zé)：
1、Physical?Integration?and?early?floorplan
2、Place?&?CTS?&?Routing
3、Partition?level?and?full?chip?level?Static?Timing?Analysis
4、Develop?custom?timing?scripts?using?tcl/primetime?for?clock?skew?analysis
5、Cross?talk?Analysis
6、Develop?and?enhance?entire?physical?design?flow?at?both?chip?and?block?level.
7、Develop?scripts?for?performing?ECO's
8、Physical?verification?such?as?DRC/LVS
9、IR/EM?analysis
任職要求：
1、BS?or?MS?in?Electrical?Engineering?or?Computer?Science
2、Above?1~3?years?of?relevant?ASIC?experience?ideally?with?a?focus?in?the?physical?implementation?and?timing?closure
3、Excellent?scripts?skills
4、Ability?to?multiplex?many?issues,?set?priorities,?and?work?in?a?team?environment
5、Keep?up?to?date?with?leading?edge?technologies
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